This disclosure relates to the methods associated with the transfer of data between a main host computer and one or more peripheral devices which operate under the protocols designated as Federal Information Protocol Standards, (FIPS).
The general environment involved herein is that shown in FIG. 1 of this disclosure which has been derived from U.S. Pat. No. 4,425,615, inventor Swenson, et al, and entitled: "Hierarchical Memory System Having Cache/Disk Subsystem with Command Queues for Plural Disks". This patent was assigned to the Sperry Corporation whose name was subsequently changed to the Unisys Corporation.
Additionally, this application is related to an application entitled "Cache Disk Subsystem Trickle" which was filed as U.S. Ser. No. 207,097 by the inventor, Robert E. Swenson, and which is now extant as U.S. Pat. No. 4,394,732.
These above-mentioned patents are considered to be incorporated herein by reference.
As delineated in the above-referenced patents, the basic environment involved in this system is one where one or more host processors, each having one or more input/output channels, communicate through one or more storage control units to utilize data recorded on a plurality of disk drives. The system provides a cache/disk subsystem which includes one or more storage control units (SCU) and one or more cache storage units (CSU) used by the storage control units as cache memory for the rotating disks. The cache store is transparent to the user who programs the processor as though the user were directly addressing the disk drives.
Through developments in the art, it has become known to provide a smaller set associative cache memory enabling a much shorter and faster access time than from the main memory. When the processor issues a main memory address, this address is utilized to access an "address descriptor table" (ADT) which is normally set with associative relationships and contains words identifying which memory addresses are present in the cache memory.
Each entry in the table (ADT) also includes information identifying certain characteristics of the data at the associated addresses. If the addressed data is present in the cache memory, then a transfer is set up between the processor and the cache memory. If the data being addressed is not present in the cache memory, then it is retrieved from the main memory, entered into the cache memory, and then accessed for transfer to the processor.
General usage existed where the cache memory and the main memory were both wholly electronic; however, subsequent use has been made of the fully associative cache memory in conjunction with disk devices. Thus the described environment involves a cache memory for use with a plurality of disk devices such that I/O requests from a host processor to a target disk device will be transferred from the cache memory immediately if the requested data is in the cache memory, or will be queued by the storage control unit (SCU) for later execution if the data requested is not in the cache memory.
The attached Acronym Glossary will indicate the meaning of the listed items.
______________________________________ ACRONYM GLOSSARY ______________________________________ ADT Address Descriptor Table AGEOLD Identifying old segment in Cache BMC Block Multiplexor Channel CQ Command Queue CSU Cache Storage Unit CTLDEV Control Device FBCADIS FIPS Block Multiplexor Channel Cache/Disk Software FILESAFE Action of returning data from Cache to Disk Memory FIPS Federal Information Processing Standards I/O Input/Output IOP Input/Output Processor LRU Least Recently Used MRU Most Recently Used NSRI Number of $egments to Roll In SB Staging Buffer SCU Storage Control Unit SDT Segment Descriptor Table SSD Solid State Disk SYSOLD Action of finding the oldest segment in Cache Memory UPDATE Action of comparing present time data with oldest time date in cache URP Unit Request Packet UST Unit Status Table WT Written-To ______________________________________
As seen in FIG. 1, the environment of this system includes first and second storage control units (SCU) 100 and 102, and a plurality of cache storage units (CSU) 104 and 106, and a plurality of rotating disk device drive units which are shown as disk drives 108 and 110. The SCU 100 and 102 are identical units, but are illustrated differently to show aspects of the details involved. With reference to SCU 100, each SCU may service up to four channels designated channels A through D. The SCU 100 includes four channel interfaces, designated channel interface A through D for interfacing channels A through D to a processor 112.sub.p and control store 112.sub.c within the SCU. Each SCU is provided with a control interface 122 for interfacing the CSU 104, and CSU 106 to the processor 112.sub.p and the control circuitry 112.sub.c and a device interface 124 interfaces the processor and control circuits 112, to the disk drives 108, 110, (disk units 0-15).
Each CSU (104, 106) may be provided with four ports designated port 0-port 3. As seen in FIG. 1, SCU 100 is connected to port 0 of each CSU, and the SCU 102 is connected to port 1 of each CSU with ports 2 and 3 being unused.
For example, a typical cache/disk subsystem includes from one to four CSU's, and the amount of cache storage can vary within a storage unit and also can vary based on the number of storage units.
As seen in FIG. 1, the CSU 104 is provided with a Segment Descriptor Table (SDT) 126 capable of storing up to 254 kilobytes of information related to identifying the data stored in cache storage. If all of the CSU's 104, 106 are "shared", then a single SDT in one CSU stores the information relating to identifying the segments of data stored in all of the CSU's.
However, if the cache memory (CSU 104, 106}is partitioned into two or more groups of CSU's, then there must be an SDT for each group. Thus, if SCU 100 is connected only to CSU 104, and SCU 102 is connected to CSU 106, then both CSU's 104 and 106 must contain an SDT, as the SDT 126, FIG. 1.
The device interface 124 in FIG. 1 operates to service a maximum of 16 disk drives, all of which are of the same type. However, it is not possible to intermix disk drives of different types in a single bank. The disk utilized by the cache/disk subsystem is designated as the 8481M which is marketed by Unisys Corporation. However, other types of disk drives may also be utilized.
The lower half of FIG. 1 illustrates the flow of data between the channels, the CSU (104, 106) and the disk drives. Generally, when a channel wishes to read or write on a disk, it issues a FIPS 97 compliant command sequence which, among other things, specifies: the operation to be performed, the address of the disk drive containing the data to be involved in the transfer, the number of blocks to be transferred, and the disk relative logical block address where transfer is to begin.
The unit of data transfer between the SCU 102 and the disks, and between the control unit and the cache, is called a "segment" when the subsystem is operating in a "cache mode". A segment contains 8,192 bytes of data. On the Unisys Series 1100 systems, only the first 8,064 bytes contain valid data. The subsystem logic does not support segments of any size other than 8,192 bytes. The segments are blocked together to optimize the staging of data.
Thus, when the channel is granted access to the SCU, as 102, the command sequence is sent from one of the channel interfaces 114, 116, 118, 120 to the processor 112.sub.p in the SCU 102. The SCU processor 112.sub.p accesses the SDT 126 through the control interface 122 for the purpose of determining if segment(s) containing the disk addresses, involved in the transfer, are presently contained in the cache memory CSU 104, 106. If the addresses to be involved in the transfer are present in the segments in cache memory (called a "hit"), the processor 112.sub.p causes the segment to be "read" from the cache memory into a staging buffer 132.
If the command from the channel interfaces 114, 116, 118, 120 specifies a "Read" operation and the requested data resides in the CSU 104, 106, the data is transferred from the CSU through the control interface 122 to the staging buffer (SB) 132 and from the SB over bus 128 (data bus) to the block MUX channel buffer (130, FIG. 4) and from the block MUX channel buffer to the channel. This constitutes a "hit".
On the other hand, if the command sequence specifies a "Write" operation, the SCU processor 112.sub.p directs the data be taken from the channel interfaces (114, 116, 118, 120) to the SB 132 and then from the SB through the control interface 122 to the CSU 104, 106.
Now, if, at the time the SCU processor 112.sub.p examines the SDT 126, it determines that the segment containing the required addresses is not resident in the cache storage, (called a "miss"), then the SCU processor 112.sub.p acts through the device interface 124 to then access the disk drive containing the required locations. The segment containing the required locations plus additional adjacent segments are then read from the disk drive through the device interface 124 to the SB 132, and then through the control interface 122 to the cache memory, CSU 104, 106. The number of segments to roll in (NSRI) is based on SCU estimation or speculation. The segment is also read from the SB 132 to the block MUX channel buffer (130, FIG. 4) and from the block MUX channel buffer to the channel.
When the device address is for a rotating disk and the subsystem is "not caching" , the SCU 102 will initiate positioning on the disk unit and return "Channel End" status. If the device address is for a rotating disk and the subsystem is "caching" and this request results in a cache "miss" condition, then the SCU 102 will place the request on the command queue and then return "Channel End" status and disconnect from the channel. The SCU 102, after disconnecting from the channel, will be prepared to accept an initial selection sequence for a different device or request number on the channel interface without presenting a control unit "busy sequence". The subsystem, when caching, will accept up to seven requests per rotating disk unit. Both of the previous cases will present "Device End" status to the LOCATE command after the unit is positioned and the unit is ready to transfer data.
The cache storage unit (CSU) can also act as a disk device known as "Solid State Disk" (SSD) which provides requested data with zero latency (no seek time). A maximum of 15 SSD's are supported.
When the device address is for a SSD (simulated in electronic memory) or if the subsystem is "caching" and the request will result in a cache "hit" condition, the SCU 102 will present "Channel End", "Device End" status, to the LOCATE command.
The above description is meant to illustrate the point that the cache storage is "transparent"to the user. Thus, the program used by the user is written as though the commands were addressing the disk drives directly, and the user is unaware of the operation of the intervening "cache memory", i.e. cache storage units 104, 106.
It may be noted that, generally, data transfers initiated by the host processor 10 do not start or finish exactly on the segment boundaries. Since the cache and the disks can only be addressed by full segments, it is necessary to first bring the entire required segment into one of the 8K-byte buffers in the control unit SCU 102, then alter or extract from this buffer the data desired, and then, if a Write command is extant, return the updated segment back to the appropriate disk device at a later time. This operation is denoted as "trickle".
For many applications, statistics indicate that if a request is received for data residing in one segment on a disk, then there is a "high probability" that a request is very soon to be made for data in segments immediately following this segment. By taking advantage of this phenomena, whenever a segment is read from disk to cache, then additional segments are read into the cache on the speculation that they also will be needed. The number that is read in, is the difference between a parameter (number of segments to roll in [NSRI]) specified by software and the number of segments rolled in as a result of "misses". For example, if a request called for three segments to be accessed, all three of which result in "misses", and also the parameter NSRI was set at four, then the number which i read in by "speculation" is 4-3=1 segment.
Because these additional segments are considered speculative and may or may not be used, they are assigned an "older" age than the segments that were actually requested. All segments in the cache are linked together by "age" in the SDT 126 called the "Segment Descriptor Table" (SDT). The links extend from the "most recently used" (MRU) segments down to the "least recently used" (LRU). Once the cache (CSU 104, 106) has been filled, segment entries are removed from the SDT, starting at the LRU entry, to make room for the new data. Each time a segment in cache is referenced by a normal Read or Write operation, its entry in the SDT is advanced to the MRU position in the "age chain".
In order to maintain available space in the cache (CSU) for new data, there is a special operation called a "trickle" which is performed by the subsystem. During periods when the control unit SCU 102 is idle, it links through the SDT 126, looking for segments that have been altered while residing in the cache and which, therefore, do not have a "current copy" residing on the disk. When a "written-to" flag is detected denoting such a condition, the corresponding segment is then written out to the appropriate disk and the flag is cleared. The segment still remains also in the cache and is available if requested by the processor (host 10), provided the "ageing process" has not replaced it with another segment. This system has been described in U.S. patent application Ser. No. 207,097 by the aforementioned Robert W. Swenson, which issued as U.S. Pat. No. 4,394,372.
When a segment is "written-to" (WT) the first time, a "time stamp" is inserted in the SDT entry. This time stamp is supplied by the software. For every Read or Write I/O request in a post-store cache mode, the time stamp and file number (for the I/O request) is included in a "SET DIAGNOSE Command" and "Define Modifiers" subcommand parameters. The time stamp entries are linked together starting with the oldest and ending with the newest. The time stamp links are used by the SCU to search for segments to "trickle". The time stamp of the oldest WT (updated) segment, together with the "AGEOLD" parameter are used to determine the execution priority of the trickle function. By periodically (when the control unit SCU 102 is idle) reading the time stamp of the oldest WT segment, the software constantly monitors the progress of trickling by the SCU 102, 100.
To aid in error recovery when an SDT error occurs, a copy of the SDT is contained in the unused space of the cache modules. This space is the remaining 128 bytes that are not normally used out of each 8,192-byte segment. If an SDT error occurs, the SCU 102 quits accepting requests from the host and returns a special status. The software then initiates the "de-stage" of all the cache segments using the SDT copy in the cache. De-staging involves transferring all written-to (WT) data from cache to the disk. This procedure allows for recovery of all data resident in the cache if an "SDT Only" error occurs.